mission

As design community is moving towards transaction level modeling, the gap with the transistor level is dramatically increasing. Still, there is a number of design challenges addressed at the transistors level as, for example, complex IO, memory block design or mixed-signal digital IPs.
Even if transistors level description can be mixed within a higher level (RTL) description for mixed level simulation, it is at the expense of a severe performance penalty. Furthermore, critical formal techniques such as assertion checking or equivalence checking can not be applied at all.

For all these situations, Heedsoft offers innovative solutions to abstract transistors descriptions and fill the gap between transistor and upper levels. Heedsoft mission is to provide advanced HDL modeling and equivalence checking solutions to this end.

  application

HDL model generation
Transistors abstraction provides a functional description of the design under verification. RTL tools can then load this abstracted model to execute the verification plan, but thousands of times faster.

HDL model validation
Existing HDL model of an IP, digital or mixed, requires verification against its transistors implementation. Equivalence checking between the HDL model and the transistors description guarantees complete and formal functional matching.

Low power design
Modern designs include dedicated transistor structures to support low power requirements. Transistors abstraction provides the mean of handling the explicit RTL functions together with the low power transistors structures behaviors.