productsTLL is a transistor abstraction tool. It transforms a complex electronic circuit (e.g. Spice CDL or Verilog netlist) into an equivalent RTL Verilog or VHDL model.
Unlike traditional abstraction tools, which are essentially based on structural recognition of predefined templates, TLL performs electrical network computations to extract functions. This characteristic brings unique accuracy and genericity to the abstraction process.
The tool is capable of detecting electrical conflicts statically with an accuracy close to what would be obtained with a dynamic analog simulation. TLL has dedicated algorithms to efficiently abstract multi-dimensional memory arrays and edge-sensitive memory points.TLL is fast, has a small memory footprint and can abstract designs with sizes up to hundreds of millions of transistors.
FlexCheck is a unique equivalence checker. FlexCheck can compare two models of any abstraction level from transistor, gates, up to RTL level, even supporting non synthesizable constructs. FlexCheck combines symbolic simulation with static formal equivalence techniques. Thus, FlexCheck technology removes some of the traditional limitations to deliver fast execution time, flexibility together with powerful debugging features.
| © Heedsoft 2012 / Legal terms | Heedsoft France +33 493 778 426 -- info(ar)heedsoft.com |