TLL 4: a revolution in transistors abstraction

New transistors abstraction algorithm

The heart of the TLL tool is based on a powerful algorithm that transforms transistors circuits into functions. Even if accurate, abstraction kernel embedded in TLL 3.x series lacks precision for timing analysis. A new algorithm has been developped, which starts from fine physical characteristics to compute functions with a very high accuracy, even for the most complex and new full custom designing styles.

Cycles replacement

Even if previous releases of TLL could recognize most of the memory points types it had been faced to in the past, some new technologies developped by the most advanced ICs developpers were reaching the limits of TLL. Heedsoft thus decided to go further. Starting from more generic concepts, we built a new algorithm in charge of the cycles elimination (for latches, oscillations, false cycles, front detectors, keepers and flip-flops). This new algorithm is able to recognize any kind of cycles, from any length, and to plug the appropriate model for it. A memory point can be made of any number of sub-cycles and still being recognized by the tool.

2-D memory arrays recognition

TLL 3.x series are able to automatically recognize memory points vectors. TLL 4 extends this powerful mechanism to 2-D arrays. This great enhancement allows automated matching by equivalence checkers between TLL abstracted model and reference golden model.

Timed abstraction

This is probably the most important evolution of the tool. Starting from technology parameters and parasitic effects (like resistive and capacitive effects), TLL 4 automatically generates verilog models with timing directives. It follows that plugging a TLL abstracted model in a digital simulator leads to timed simulations, with very accurate simulation time (nearly the same than an analog simulator), but thousands of times faster...